The development of computer graphics systems creates the need for fast memories capable of storing huge amounts of data, such as 3-D graphics data. Among such memories are cached memories developed to improve DRAM main memory performance by utilizing a faster SRAM cache memory for storing the most commonly accessed data. For example, U.S. Pat. No. 5,566,318 discloses an enhanced DRAM that integrates a SRAM cache memory with a DRAM on a single chip. Sense amplifiers and column write select registers are coupled between the SRAM cache and the DRAM memory array. A column decoder is associated with the SRAM cache for providing access to the desired column of the SRAM. A row decoder is associated with the DRAM memory array to enable access to particular rows of the DRAM. Input/output control and data latches receive data from the SRAM to provide data output via data input/output lines. The current row of data being accessed from the DRAM memory array is held in the SRAM cache memory. Should a cache "miss" be detected, the entire cache memory is refilled from the DRAM memory array over a DRAM-to-cache memory bus.
As a way of improving speed and performance of a RAM, a dual-port RAM has been developed which enables two separate input/output ports to access the memory array. However, the dual-port RAM cannot provide effective control of data input and output, because its ports are not interchangeable. For example, data traffic cannot be redistributed between the ports, when one of them is overloaded and the other is underloaded.
Accordingly, it would be desirable to provide a multi-port RAM chip having interchangeable ports.
Also, it would be desirable to provide a data masking system that enables a user to prevent specific unnecessary bits of data from being written into a SRAM cache memory or a DRAM main memory when any of data ports performs a write access to a memory system. As a result, the performance of the memory would be enhanced.
Moreover, it would be desirable to provide a data masking system that allows a user to load mask data either from both data ports or from any one of the data ports.